Comparator circuits are well known in the art of integrated circuits. In it simplest form, a comparator circuit compares two input voltages, and produces a single output voltage reflecting which of the two input voltages is larger. For example, in a simple comparator circuit, if Vin1>Vin2, then the output might equal a high logic state, i.e., a logic ‘1.’ If Vin1<Vin2, then the output would equal a low logic state, i.e., a logic ‘0.’ This comparison of the two voltages can then be used in various ways to perform useful functions on the integrated circuit. For example, in a Dynamic Random Access Memory (DRAM) circuit, a comparator is used to compare a reference voltage to an output voltage produced from an output driver model, with the results of the comparison used to generate control signals for the output drivers coupled to the I/O bond pads to adjust their output impedances. (For further details regarding the use of a comparator to calibrate output impedances, see U.S. patent application Ser. No. 11/210,009, filed Aug. 22, 2005, which is incorporated herein by reference in its entirety). In any event, this is just one example in which a comparator circuit can be used, and this disclosure is not limited to the use of a comparator in any particular environment.
FIG. 1 illustrates a prior art comparator circuit 10 used for output impedance calibration. This prior art comparator 10 is more complicated than that just explained in that it produces two outputs, DEC and INC as is useful in the unique environment of output impedance calibration. The comparator compares two input voltages, Vin and Vref, and, generally speaking, when Vin>Vref, DEC is asserted, which reflects that Vin is too high and is preferably decreased. Otherwise, when Vin<Vref, INC is asserted, reflecting that Vin is too low and is preferably increased. Because operation of the prior art comparator circuit will be clear to those of skill in the art, the circuitry of FIG. 1 is not explained in much detail. However, one skilled will recognize that the circuitry 10 comprises three stages: an amplifier stage 12; a latch stage 14; and an output buffer stage 16.
One circuit element particularly worthy of note is the differential sense amplifier (DSA) 20 that comprises a portion of the amplifier stage 12. As is known, the DSA 20 compares the two input voltages, Vin and Vref, and output voltages on nodes A and B indicative of the comparison. However, as used in the disclosed prior art comparator circuit 10, the DSA 20 is not ideal, as shown in FIG. 2. FIG. 2 shows the comparator circuit 10 of FIG. 1 as simulated under normal conditions (e.g., Vcc=1.5V; temperature=25 degrees C.). As simulated, the Vref was held to a midpoint voltage (600 mV) while Vin was gradually transitioned around this value. Specifically, as shown, Vin was ramped from 400 mV to 800 mV over a period of 500 nanoseconds, and then ramped back down to 400 mV again by 1000 nanoseconds, with the result that Vin=Vref at 250 and 750 microseconds.
Ideally, the prior art comparator circuit 10 should show a simulated output in which INC is a logic ‘1’ (i.e., Vcc) from 0 to 250 nanoseconds and from 750 to 1000 nanoseconds (when Vin<Vref), and in which DEC is a logic ‘0’ from 250 to 750 nanoseconds (when Vin>Vref). But, as simulated, the actual results deviate from this ideal. As shown in FIG. 2, while INC goes low at approximately 250 nanoseconds as it should, DEC does not go high until approximately 280 nanoseconds, resulting in an approximately 30 nanosecond gap Δ in which the output of the comparator 10 is indeterminate. Such a gap Δ is obviously not ideal, as valid inputs to the circuit do not timely produce valid outputs.
Moreover, even if it is assumed that the gap Δ is permissible, the circuit 10 should still perform with appropriate symmetry. In other words, if DEC. does not go high until approximately 280 nanoseconds, i.e., when Vin is some offset higher than Vref, symmetry would dictate that DEC should go low when Vin falls beneath that offset, i.e., at approximately 720 nanoseconds. However, as can be seen, such symmetry is not present: DEC does not fall at approximately 720 nanoseconds, but instead falls at approximately 750 nanoseconds. These non-symmetries in the comparator circuit 10 are the result of unwanted hysteresis in the circuit.
Ultimately, the non-ideal performance of the comparator circuit 10 (indeterminate outputs; hysteresis) result from the use of the DSA 20 in the circuit. As one skilled in the art will appreciate, a DSA will not work particularly well, or quickly, when the difference in potential between the two inputs (Vin, Vref) is small, e.g., on the order of 10 mV. The result of such a small differential input voltage is that it takes the DSA 20 longer to reliably establish an output voltage indicative of the comparison. Moreover, when the DSA 20 has been operated to output one state, it then becomes slightly more difficult to transition to the other state, resulting in the hysteresis effect just discussed.
In any event, such shortcomings from the comparator circuit of the prior art are unfortunate, and hamper the utility of the circuit in many applications, such as output impedance calibration, in which the output of the comparison of the two inputs must be made quickly and reliably, even when the differential between the two inputs is very small. Hence, it is a goal of this disclosure to provide a solution to this problem.